CadenceCONNECT:
Advancing Digital Design and Signoff Excellence
Radisson Blu Hotel, Marathahalli ORR, Bengaluru
Summary
Achieving optimal power, performance, and area (PPA) while managing increasingly complex designs is more challenging than ever. We are thrilled to invite you to CadenceCONNECT: Advancing Digital Design and Signoff Excellence, a flagship event tailored for senior chip designers, design engineers, and engineering managers.
This full-day, in-person seminar will be packed with insights from the Cadence R&D team, the masterminds behind our cutting-edge technologies. Learn from the experts as they guide you through the complete RTL to GDS flow, spotlighting the latest advancements in synthesis, implementation, and signoff technologies.
Highlights you'll experience:
- Discover how Cadence Cerebrus, our AI/ML technology, is revolutionizing PPA and productivity
- Gain exclusive knowledge to tackle complex designs for full flow power, performance, area, and TAT improvements
- Interact with senior leaders and enhance your expertise in digital design and signoff solutions
Event Details
Date: April 3, 2025
Time: 9:30am – 4:30pm IST
Venue: Radisson Blu Hotel, Marathahalli Outer Ring Road, Bangalore
Agenda
| Time | Topic | Presenter |
| 9:30 - 10:00 | Cadence Keynote | Chin-Chi Teng, PhD., Sr VP and GM - Digital and Signoff Group, Cadence |
| 10:00 - 10:30 | Guest Keynote | Viji Ranganna, Director, Silicon Engineering, Google |
| 10:30 - 10:45 | Tea Break | |
| Implementation Track | ||
| 10:45 - 11:45 | Power Optimization Using Advanced Techniques and Software Enhancements by Keeping a Check on Frequency | Savita Chaudhary, Product Engineering Director, Cadence Sharad Bhushan Jha, Sr Software Architect, Cadence Roja Veeramachaneni, Sr Product Engineering Architect, Cadence |
| 11:45 - 12:45 | Enhancing Frequency with Advanced Techniques and the Latest Software Updates for High-Performance Designs | Ravi Andrew, Product Engineering Group Director, Cadence Lokeswara Korlipara, VP Research & Development, Cadence Bharat Chhabra, Product Engineering Architect, Cadence Roja Veeramachaneni, Sr Product Engineering Architect, Cadence |
| 12:45 - 13:45 | Lunch Break | |
| 13:45 - 14:45 | How to Achieve Best TAT for Multimillion Designs | Ravi Andrew, Product Engineering Group Director, Cadence Sharad Bhushan Jha, Sr Software Architect, Cadence Roja Veeramachaneni, Sr Product Engineering Architect, Cadence |
| 14:45 - 15:30 | Next Generation Cerebrus: AI-Driven Multi-Block / SoC Design Platform | Sreeram Chandrasekhar, Product Engineering Group Director, Cadence |
| 15:30 - 15:45 | Cadence Cerebrus AI Studio: Pervasive Intelligence Productivity Boost with PPA Gains | Rajesh Kumar Bommana, Assistant Director, Samsung |
| 15:45 - 16:45 | Optimizing Smart Hierarchical Flows for Enhanced Runtime, Accuracy, and Performance | Ravi Andrew, Product Engineering Group Director, Cadence Sharad Bhushan Jha, Sr Software Architect, Cadence Roja Veeramachaneni, Sr Product Engineering Architect, Cadence |
| Signoff Track | ||
| 10:45 - 11:30 | Tempus: 2B+ Instances Full-Chip Signoff for Hierarchical Designs with SmartScope and Tempus DSTA + Roadmap | Prashant Sethia, Sr Software Engineering Group Director, Cadence |
| 11:30 - 12:15 | Full Chip Signoff for Multibillion Instance Count Designs Using Distributed STA + SmartScope and Cadence Certus Closure Solution | Nagabharana Teeka, Senior Director, Samsung |
| 12:15 - 12:45 | 3D-IC Technologies and Roadmap | Arvind Veeravalli, Sr Software Architect, Cadence |
| 12:45 - 13:30 | Lunch Break | |
| 13:30 - 14:00 | Timing Signoff Challenges for Advanced Process Nodes | Shitanshu Tiwari, Sr. Director, Technology, Qualcomm |
| 14:00 - 14:45 | Optimization and Closure for Block-Level and Subsystem-Level With Tempus ECO and Cadence Certus Closure Solution | Sourav Sircar, Sr Software Engineering Group Director, Cadence |
| 14:45 - 15:15 | Optimizing ECO Flow for Faster SoC Turnaround Time | Gangadhar Naik, Sr Principal Engineer Manager, Marvell |
| 15:15 - 15:45 | Tempus Design Robustness (DRA ) Suite and Vmin Analysis | Manuj Verma, Software Engineering Group Director, Cadence |
| 15:45 - 16:15 | Accelerate IR Signoff with Voltus InsightAI and Voltus XM | Rajat Chaudhry, Product Management Group Director, Cadence |
| 16:15 - 16:45 | Pegasus InDesign Flow/Cloud Signoff | Pooja Pangoria, Software Engineering Group Director, Cadence |
